-#if !defined(__msp430_headers_timerb_h__)
-#define __msp430_headers_timerb_h__
+#if !defined(__MSP430_HEADERS_TIMERB_H__)
+#define __MSP430_HEADERS_TIMERB_H__
/* timerb.h
*
* (c) 2002 by M. P. Ashton <data@ieee.org>
* Originally based in part on work by Texas Instruments Inc.
*
- * $Id: timerb.h,v 1.11 2006/04/19 20:09:52 cliechti Exp $
+ * 2009-10-08 - modifications by J.M.Gross <mspgcc@grossibaer.de>
+ * - added basic support for TB7 on MSP430F54xx
+ *
+ * $Id: timerb.h,v 1.12 2008/10/09 15:00:14 sb-sf Exp $
*/
/* Switches:
-__MSP430_HAS_TB7__ - if timer B has 7 capture/compare registers (default is 3)
-
+__MSP430_HAS_TB7__ - if timer B has 7 capture/compare registers (default is 3)
+__MSP430_HAS_TB7_5__ - if timer B is part of Series 5 devices (and has 7 CC registers)
+__MSP430_TB7_BASE__ - base address TB7_5
*/
+#if defined (__MSP430_HAS_TB7_5__)
+
+#define TBCTL_ __MSP430_TB7_BASE__ + 0x00 // Timer B Control
+sfrw (TBCTL,TBCTL_);
+#define TBCCTL0_ __MSP430_TB7_BASE__ + 0x02 // Timer B Capture/Compare Control 0
+sfrw (TBCCTL0,TBCCTL0_);
+#define TBCCTL1_ __MSP430_TB7_BASE__ + 0x04 // Timer B Capture/Compare Control 1
+sfrw (TBCCTL1,TBCCTL1_);
+#define TBCCTL2_ __MSP430_TB7_BASE__ + 0x06 // Timer B Capture/Compare Control 2
+sfrw (TBCCTL2,TBCCTL2_);
+#define TBCCTL3_ __MSP430_TB7_BASE__ + 0x08 // Timer B Capture/Compare Control 3
+sfrw (TBCCTL3,TBCCTL3_);
+#define TBCCTL4_ __MSP430_TB7_BASE__ + 0x0A // Timer B Capture/Compare Control 4
+sfrw (TBCCTL4,TBCCTL4_);
+#define TBCCTL5_ __MSP430_TB7_BASE__ + 0x0C // Timer B Capture/Compare Control 5
+sfrw (TBCCTL5,TBCCTL5_);
+#define TBCCTL6_ __MSP430_TB7_BASE__ + 0x0E // Timer B Capture/Compare Control 6
+sfrw (TBCCTL6,TBCCTL6_);
+#define TBR_ __MSP430_TB7_BASE__ + 0x10 // Timer B
+sfrw (TBR,TBR_);
+#define TBCCR0_ __MSP430_TB7_BASE__ + 0x12 // Timer B Capture/Compare 0
+sfrw (TBCCR0,TBCCR0_);
+#define TBCCR1_ __MSP430_TB7_BASE__ + 0x14 // Timer B Capture/Compare 1
+sfrw (TBCCR1,TBCCR1_);
+#define TBCCR2_ __MSP430_TB7_BASE__ + 0x16 // Timer B Capture/Compare 2
+sfrw (TBCCR2,TBCCR2_);
+#define TBCCR3_ __MSP430_TB7_BASE__ + 0x18 // Timer B Capture/Compare 3
+sfrw (TBCCR3,TBCCR3_);
+#define TBCCR4_ __MSP430_TB7_BASE__ + 0x1A // Timer B Capture/Compare 4
+sfrw (TBCCR4,TBCCR4_);
+#define TBCCR5_ __MSP430_TB7_BASE__ + 0x1C // Timer B Capture/Compare 5
+sfrw (TBCCR5,TBCCR5_);
+#define TBCCR6_ __MSP430_TB7_BASE__ + 0x1E // Timer B Capture/Compare 6
+sfrw (TBCCR6,TBCCR6_);
+#define TBEX0_ __MSP430_TB7_BASE__ + 0x20 // Timer B Expansion Register 0
+sfrw (TBEX0,TBEX0_);
+#define TBIV_ __MSP430_TB7_BASE__ + 0x2E // Timer B Interrupt Vector Word
+sfrw (TBIV,TBIV_);
+
+
+#define TBCLGRP1 0x4000 /* Timer B compare latch load group 1 */
+#define TBCLGRP0 0x2000 /* Timer B compare latch load group 0 */
+#define CNTL1 0x1000 /* Counter length 1 */
+#define CNTL0 0x0800 /* Counter length 0 */
+#define TBSSEL1 0x0200 /* Clock source 1 */
+#define TBSSEL0 0x0100 /* Clock source 0 */
+#define TBCLR 0x0004 /* Timer B counter clear */
+#define TBIE 0x0002 /* Timer B interrupt enable */
+#define TBIFG 0x0001 /* Timer B interrupt flag */
+
+#define TBSSEL_0 (0<<8) /* Clock source: TBCLK */
+#define TBSSEL_1 (1<<8) /* Clock source: ACLK */
+#define TBSSEL_2 (2<<8) /* Clock source: SMCLK */
+#define TBSSEL_3 (3<<8) /* Clock source: INCLK */
+#define CNTL_0 (0<<11) /* Counter length: 16 bit */
+#define CNTL_1 (1<<11) /* Counter length: 12 bit */
+#define CNTL_2 (2<<11) /* Counter length: 10 bit */
+#define CNTL_3 (3<<11) /* Counter length: 8 bit */
+#define TBCLGRP_0 (0<<13) /* Timer B Group: 0 - individually */
+#define TBCLGRP_1 (1<<13) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define TBCLGRP_2 (2<<13) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
+#define TBCLGRP_3 (3<<13) /* Timer B Group: 3 - 1 group (all) */
+
+/* Additional Timer B Control Register bits are defined in Timer A */
+
+#define CLLD1 0x0400 /* Compare latch load source 1 */
+#define CLLD0 0x0200 /* Compare latch load source 0 */
+
+#define CLLD_0 (0<<9) /* Compare latch load source 0 - immediate */
+#define CLLD_1 (1<<9) /* Compare latch load source 1 - TBR counts to 0 */
+#define CLLD_2 (2<<9) /* Compare latch load source 2 - up/down */
+#define CLLD_3 (3<<9) /* Compare latch load source 3 - TBR counts to TBCTL0 */
+
+/* Aliases by mspgcc */
+#define TBSSEL_TBCLK TBSSEL_0
+#define TBSSEL_ACLK TBSSEL_1
+#define TBSSEL_SMCLK TBSSEL_2
+#define TBSSEL_INCLK TBSSEL_3
+
+#define CNTL_16 CNTL_0
+#define CNTL_12 CNTL_1
+#define CNTL_10 CNTL_2
+#define CNTL_8 CNTL_3
+
+
+/* on newer devices, TIMERA0, TIMERA1 and TIMERB have identical TIV registers */
+#if !defined(TIV_NONE) /* in case already defined by TIMERA */
+ #define TIV_NONE 0x00 /* No interrupt pending */
+ #define TIV_CCR1 0x02 /* Capture/compare 1 TACCR1 CCIFG Highest */
+ #define TIV_CCR2 0x04 /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR3 0x06 /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR4 0x08 /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR5 0x0A /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_CCR6 0x0C /* Capture/compare 2 TACCR2 CCIFG */
+ #define TIV_OVERFLOW 0x0E /* Timer overflow TAIFG Lowest */
+#endif
+
+#else /* not a series 5 device */
+
#define TBIV_ 0x011E /* Timer B Interrupt Vector Word */
sfrw(TBIV,TBIV_);
#define TBCTL_ 0x0180 /* Timer B Control */
#endif
-#ifndef _GNU_ASSEMBLER_
+#ifndef __ASSEMBLER__
/* Structured declaration */
typedef struct {
volatile unsigned
#endif /*__MSP430_HAS_TB7__B7*/
#define TBIV_OVERFLOW 0x0E /* Timer overflow TBIFG Lowest */
-#endif
+#endif /* old TimerB */
+
+#endif /* __MSP430_HEADERS_TIMERB_H__ */
projects / msp430-libc.git / blobdiff